What is the clock-cycle time in a non-pipelined and a pipelined processor?

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1

Consider a pipeline with the following stage latencies

IF ID EX MEM WB
100ps 100ps 250ps 150ps 50ps
  1. What is the clock-cycle time in a non-pipelined and a pipelined processor?
  2. What is the total latency of a LW instruction in a non-pipelined and a pipelined processor?
  3. If we can split one stage of the pipelined datapath into two new stages, each with half latency of the original stage, which stage should be split and what is the new clock-cycle time of the processor?